About

Recent papers from Meta (Facebook) and Google [1-3] have created a major concern about data integrity in large-scale computing in cloud data centers. The term “mercurial cores” has been coined [2] to refer to errant processor cores that have been clearly diagnosed as being the source of generating silent data errors – and recent panels (as referred to above) have brought together experts from cloud service providers and processor chip designers with the objective of raising awareness of this acute problem, and also encouraging leading edge research to devise affordable chip and system-level mitigation solutions. In addition to such data integrity concerns, the rise of data security and privacy breaches in cloud computing environments has accelerated research and development of practical solutions that enable computing with encrypted data (e.g., advanced cryptographic methods like Fully Homomorphic Computing or FHE); e.g., recent papers [4-6].

This workshop (DISCC-2022) proposes to bring together aspects of data integrity and security in a single, unified forum. The workshop will comprise a keynote speech, several contributed papers and, time permitting, a closing panel session involving leading edge experts in data integrity and security in a hyper-scale cloud computing setting. Potential speakers are encouraged to submit an extended abstract (1-2 pages) highlighting the key contributions in the light of the above-stated technical scope of the problem. Solution approaches at the algorithm, software/firmware and/or hardware level are encouraged for early dissemination and discussion in a workshop setting.

Topics of interest include but are not limited to:

  • Testing (including detection and/or diagnosis) of silent data errors (SDEs) for plaintext and/or HE-mode ciphertext computation.
  • Detection and mitigation of malicious attacks that can lead to SDEs.
  • Privacy-preserving data-secure computation: novel software and/or hardware solutions.
  • Characterization of HE workloads for “discovery” of hardware acceleration primitives.
  • Simulation and/or emulation based modeling methods to evaluate DISCC domain software-hardware solutions.
  • Modeling of cloud-edge solutions for specific safety-, security- and/or privacy-critical applications: e.g., autonomous vehicles, internet banking, credit card fraud detection, etc.

References

  1. H. D. Dixit, S. Pendharkar, M. Beadon, C. Mason, T. Chakravarthy, B. Muthiah, S. Sankar, “Silent data corruptions at scale,” https://arxiv.org/abs/2102.11245 , Feb. 22, 2021.
  2. P. H. Hochschild, R. Govindaraju, D. E. Culler, “Cores that don’t count,” HotOS ’21, May 31 – June 2, 2021, Ann Arbor MI. https://doi.org/10.1145/3458336.3465297.
  3. D. F. Bacon, “Detection and prevention of silent data corruption in an exabyte-scale database system,” The 18th IEEE Workshop on Silicon Errors in Logic – System Effects, IEEE (2022)
  4. N. Samardzic, A. Feldman, A. Krastev, N. Manohar, S. Devadas, K. Edefravy, C. Peikert, D. Sanchez, “CraterLake: A Hardware Accelerator for Efficient Unbounded Computation on Encrypted Data,” Proc. International Symp. on Computer Architecture (ISCA), June 2022.
  5. S. Kim, J. Kim, M. J. Kim, W. Jung, J. Kim, M. Rhu, J. H. Ahn, “BTS: An Accelerator for Bootstrappable Fully Homomorphic Encryption,” Proc. International Symp. on Computer Architecture (ISCA), June 2022.
  6. A. Feldmann, N. Samardzic, A. Krastev, S. Devadas, R. Dreslinski, K. Eldefrawy, N. Genise, C. Peikert, D. Sanchez, “F1: A Fast and Programmable Accelerator for Fully Homomorphic Encryption (Extended Version),” https://arxiv.org/abs/2109.05371 ; also appeared at MICRO, Oct. 2021.


Contact

Call for Contributions

Submitted manuscripts must be in English of up to 2 pages (with same formatting guidelines as main conference). Submissions should be submitted to the following link by September 16th September 23rd (deadline extended) , 2022. If you have questions regarding submission, please contact us: info@disccworkshop.org

Organizing Committee

  • Pradip Bose (IBM)
  • Augusto Vega (IBM)
  • Jennifer Dworak (SMU)
  • Subhashish Mitra (Stanford)
  • Chris Wilkerson (Intel)
  • Ramon Bertran (IBM)
  • Nathan Manohar (IBM)
  • Nir Drucker (IBM)
  • Subhankar Pal (IBM)
  • David Trilla (IBM)

Advisory Program Committee

  • Peter H. Hochschild (Google)
  • Jeffrey Hicks (Intel)
  • Rob Chappell (Microsoft)
  • Harish D. Dixit (Meta)
  • Karthik Swaminathan (IBM)
  • Omri Soceanu (IBM)
  • Ambar Sarkar (NVIDIA)
  • Shawn Blanton (CMU)
  • Sarita Adve (UIUC)

Paper Submission Deadline
September 16th, 2022
September 23 rd

Notification Date
September 23rd, 2022
Setpember 26th

Workshop Date
October 2nd, 2022

Keynote Speakers

Circuit Structures for Enhancing Efficient Defect Detection

Jennifer Dworak (SMU)

Jennifer Lynn Dworak is a Professor in the Department of Electrical and Computer Engineering at Southern Methodist University. Her research interests include manufacturing test, the reliability of digital circuits and systems, and hardware security. Her research is currently funded by the National Science Foundation and the Semiconductor Research Corporation, and she is a recipient of an NSF CAREER Award and a 2012 Ralph E. Powe Junior Faculty Enhancement Award funded by Oak Ridge Associated Universities. She is an author on multiple technical articles, including two papers that won a Best Paper Award from the VLSI Test Symposium and a paper that won a TTTC Naveena Nagi Award. She has also given over 30 invited talks and been an invited panelist at technical meetings throughout the world. Jennifer holds PhD, MS, and BS degrees in electrical engineering from Texas A&M University in College Station, TX.

An Architecture to Accelerate Computation on Encrypted Data

Daniel Sanchez (MIT)

Daniel Sanchez is an Associate Professor at MIT's Electrical Engineering and Computer Science Department and a member of the Computer Science and Artificial Intelligence Laboratory. He works in computer architecture and computer systems. His current research focuses on large-scale multicores with hundreds to thousands of cores, scalable and efficient memory hierarchies, architectures with quality-of-service guarantees, and scalable runtimes and schedulers. Before joining MIT in September 2012, He earned a Ph.D. in Electrical Engineering from Stanford University, where he worked with Professor Christos Kozyrakis. Daniel Sanchez has also received an M.S. in Electrical Engineering from Stanford (2009) and a B.S. in Telecommunications Engineering from the Technical University of Madrid, UPM (2007).

Program

(all times are in Central Time)
1Hybrid talks will happen live on-site and through webex, link will be emailed prior to the workshop
Recording of the talks will be made available under request: Email info@disccworkshop.org to request the video recordings

October 2nd, 2022
8:30 -8:40am Welcome Remarks
8:40 - 09:20am Keynote 1: Circuit Structures for Enhancing Efficient Defect Detection - Hybrid1
Jennifer Dworak (SMU)
09:20 - 09:40am Talk 1: Efficient Runtime Mercurial Core Detection with Core-Specific Test Case Synthesis
Jiacheng Ma (University of Michigan)
09:40 - 10:00am Talk 2: Tolerate Silent Data Errors with Coded Computation
Gefei Zuo (University of Michigan)
10:00 - 10:15am Break
10:15 - 10:55am Keynote 2: An Architecture to Accelerate Computation on Encrypted Data - Hybrid1
Daniel Sanchez (MIT)
10:55 - 11:15am Talk 3: Prune, Permute and Expand: Efficient Machine Learning under Non-Client-Aided Homomorphic Encryption
Subhankar Pal (IBM Research)
11:15- 11:35am Talk 4: Characterizing Memory Side Channels in FHE Applications
Asmita Pal (University of Wisconsin-Madison)
11:35 - 12:15pm Open Mic: Discussion on Data Integrity and Secure Cloud Computing - Hybrid1
Confirmed Speakers (5 minutes each) : Moderated by IBM Organizers
Rama Govindaraju (Google): Rama is a Director of Engineering at Google where he leads the Systems Infrastructure Performance Engineering team. Prior to that Rama was a Distinguished Engineer at IBM responsible for leading the Software Architecture at IBM's Supercomputing Lab where he led the development of 5 generations of Supercomputers. Prior to that Rama received his MS and Phd in Computer Science from Rensselaer Polytechnic Institute in New York and BE in Computer Science from BIT Mesra, Ranchi, India.
Sreejit Chakravarty (Intel) : Dr. Sreejit Chakravarty is currently a Principal Engineer at Intel Corporation. His current responsibilities include die-disaggregation and interconnect testing, silent data error and functional safety. Prior to that he was an Associate professor of Computer Science where his work was funded by multiple National Science Foundation Grants.
Subhashish Mitra (Stanford): Subhasish Mitra is Professor of Electrical Engineering and of Computer Science at Stanford University. He directs the Stanford Robust Systems Group, leads the Computation Focus Area of the Stanford SystemX Alliance, and is a member of the Wu Tsai Neurosciences Institute. His research ranges across Robust Computing, NanoSystems, Electronic Design Automation (EDA), and Neurosciences

Organizers

Pradip Bose is a Distinguished Research Scientist and manager of Efficient and Resilient Systems at IBM T. J. Watson Research Center. He has over 39 years of experience at IBM and was a member of the pioneering RISC super scalar project at IBM (a pre-cursor to the first RS/6000 system product). He holds M.S. and Ph.D. degrees from University of Illinois at Urbana-Champaign. He is a member of IBM’s elite Academy of Technology and he is a Fellow of the IEEE.

Jennifer Dworak is a Professor of Electrical and Computer Engineering at Southern Methodist University. She holds M.S. and Ph.D degrees from Texas A&M University. Her research areas of expertise and interest include hardware security and reliability testing of integrated circuits.

Nathan Manohar is a Research Scientist in Cryptography, Security, and Privacy and a member of the Cryptography Research Group at the IBM T.J. Watson Research Center. His main research interests are cryptography, computer security, and, more broadly, theoretical computer science. He is particularly interested in fully homomorphic encryption, secure multi-party computation, and functional encryption. He recently received his PhD in Computer Science from UCLA and joined IBM in 2021.

Subhasish Mitra is a Professor (Depts. of Electrical Engineering and Computer Science) at Stanford University, where he leads the Robust Systems Group (among several other leadership roles). Among his many achievements, he won the IEEE Computer Society Harry H. Goode Memorial Award “for sustained contributions to design and test of computing systems in established and emerging technologies,” in 2022. He is a Fellow of the IEEE and of the ACM.

Chris Wilkerson is a Principal Engineer at Intel Corporation. Chris has 12 years of experience at Intel including 10 years at different Intel research labs, and 2 in the product product micro-architecture team. His areas of expertise include: circuits, processor design, micro-architecture, architecture. In particular, his specialties are: low voltage circuits, low voltage micro architecture, low power, reliable design, out-of- order processor design with particular focus on branch prediction, runahead processing, cache design, cache replacement algorithms, etc.

Ramon Bertran is a Research Staff Member in the Efficient and Resilient Systems Research Group at IBM T. J. Watson Research Center. He received the PhD degree in Computer Architecture, Networks and Systems from Polytechnic University of Catalonia (UPC) in 2014. Ramon has over 10 years of experience at IBM and is involved in research and development work in the area of power-aware and resilient computer architectures and systems. He contributed to the areas of power/energy modeling and characterization using automatic microbenchmarking for IBM's p/z/ and BlueGene processors and he is the lead developer of Microprobe: a micro-architecture aware microbenchmark generator framework used to support the works on power/performance/reliability characterization.

Karthik Swaminathan is a research staff member at the Efficient and Resilient Systems Group at the IBM T.J Watson Research Center. His research has a broad, cross-layer scope examining circuit, architecture and application level optimizations for improving the reliability and energy efficiency of multi core systems and accelerators. He also works on characterizing performance and reliability of IBM server-class and mainframe processors at various stages of design. He holds a PhD from Penn State University.

Subhankar Pal is a Postdoctoral Researcher in the Efficient and Resilient Systems group at IBM T. J. Watson Research Center. His current research is focused on hardware acceleration for domain-specific and energy efficient systems. He holds a Ph.D. and M.Sc. from the University of Michigan. His Ph.D. thesis looked at designing a reconfigurable, software-defined hardware solution that balances programmability with energy efficiency. Prior to that, Subhankar was with NVIDIA, where he worked on pre-silicon verification and bring-up of multiple generations of GPUs.

David Trilla is a Post-doctoral Researcher at IBM T. J. Watson Research Center. He has worked on real-time systems and current research interests include security and agile hardware development. He obtained his Ph.D. at the Barcelona Supercomputing Center (BSC) granted by the Polytechnic University of Catalonia (UPC), Spain.

Augusto Vega is a Research Staff Member at IBM T. J. Watson Research Center involved in research and development work in the areas of highly-reliable power-efficient embedded designs, cognitive systems and mobile computing. He holds M.S. and Ph.D. degrees from Polytechnic University of Catalonia (UPC), Spain.

Registration

DISCC will be held in conjunction with the 55th International Symposium on Microarchitecture (MICRO 2022). Refer to the main venue to continue with the registration process.

Event Location

Westin Chicago River North, Chicago, Illinois, USA